The present invention is related to event synchronization, and more particularly to systems and methods for synchronizing one signal to another signal in a semiconductor device.
Synchronizing one electrical signal to another often involves applying the signal to a data input of a flip-flop, and clocking the flip-flop using a clock to which the signal is to be synchronized. The signal to be synchronized generally must be applied to the data input of the flip-flop for a defined period before the clock transitions (i.e., setup time), and must remain for a defined period after the clock transitions (i.e., hold time). By assuring that the setup and hold times are met, predictable circuit operation is achieved.
In some cases, a delay lock loop circuit has been used to delay a signal in relation to a synchronizing clock to assure that setup and hold times are met. Such delay lock loops may be iteratively updated until a desired delay is achieved. Various implementations of delay lock loop circuits, however, may incur clock glitches when an iterative update is occurring. Such glitches can at time lead to circuit errors.
Thus, for at least the aforementioned reasons, there exists a need in the art for advanced systems and devices for signal synchronization.